A CMOS imager includes a focal plane array of pixel circuits, each one of the pixels including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel has a readout circuit that includes at least an output field effect transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of an output transistor, typically a source follower transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference. A row select transistor may also be employed to gate the pixel output.
In a CMOS imager, the active elements of a pixel perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) selection of a pixel for readout; and (5) output and amplification of a signal representing pixel charge. The charge at the storage region is typically converted to a pixel output voltage by the capacitance of the storage region and a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc.
FIG. 1 illustrates a block diagram for a CMOS imager 10. The imager 10 includes a pixel array 20. The pixel array 20 comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array 20 are all turned on at the same time by a row select line and the pixel signals of each column are selectively output onto output lines by a column select line. A plurality of row and column select lines are provided for the entire array 20.
The row lines are selectively activated by the row driver 32 in response to row address decoder 30 and the column select lines are selectively activated by the column driver 36 in response to column address decoder 34. Thus, a row and column address is provided for each pixel. The CMOS imager 10 is operated by the control circuit 40, which controls the address decoders 30, 34 for selecting the appropriate row and column select lines for pixel readout, and row and the column driver circuitry 32, 36, which apply driving voltage to the drive transistors of the selected row and column select lines.
Each column contains readout and correlated double sampling (CDS) circuitry 38 associated with the column driver 36 that reads a pixel reset signal Vrst and a pixel image signal Vsig for selected pixels of each column. A differential signal (e.g., Vrst−Vsig) is produced by differential amplifiers contained in the readout and correlated double sampling circuitry 38 for each pixel and is digitized by an analog-to-digital converter 100 (ADC). The analog-to-digital converter 100 supplies the digitized pixel signals to an image processor 50, which forms a digital image output.
The signals output from the pixels of the array 20 are analog voltage signals. These signals must be converted from analog to digital for further processing. Thus, the analog signals are sent to the analog-to-digital converter 100. In a column parallel readout architecture, each column is connected to its own respective analog-to-digital converter 100.
There are many different types of analog-to-digital converters that may be used in an imager 10. One well known analog-to-digital converter is a cyclic analog-to-digital converter. A conceptual diagram of a cyclic analog-to-digital converter 100 is illustrated in FIG. 2. In the illustrated example, the cyclic analog-to-digital converter 100 contains two stages 101, 111. The first stage 101 includes a sample and hold circuit (S&H) 102, a sub-ADC 104 (e.g., a flash converter with a few output bits), a digital-to-analog converter (DAC) 106, a summation circuit 108 and a multiplier 110 (e.g., an amplifier). The input of the sample and hold circuit 102 is connected to a switch 103; in one switch position, the input of the sample and hold circuit 102 is connected to an analog input voltage VIN and in a second switch position, the input of the sample and hold circuit 102 is connected to the output of the second stage 111. The switch 103 is controlled by a START signal. The output of the sample and hold circuit 102 is connected to a positive input of the summation circuit 108 and the input of the sub-ADC 104. The output of the sub-ADC 104 is connected to the digital-to-analog converter 106. The output of the digital-to-analog converter 106 is connected to a negative input of the summation circuit 108. The output of the summation circuit 108 is connected to the multiplier 110.
The second stage 111 includes a sample and hold circuit (S&H) 112, a sub-ADC 114 (e.g., a flash converter with a few output bits), a digital-to-analog converter (DAC) 116, a summation circuit 118 and a multiplier 120 (e.g., an amplifier). The input of the sample and hold circuit 112 is connected to the output of the first stage 101. The output of the sample and hold circuit 112 is connected to a positive input of the summation circuit 118 and the input of the sub-ADC 114. The output of the sub-ADC 114 is connected to the digital-to-analog converter 116. The output of the digital-to-analog converter 116 is connected to a negative input of the summation circuit 118. The output of the summation circuit 118 is connected to the multiplier 120.
When the START signal is high, the input voltage VIN to be converted is connected to the input of the first stage 101; otherwise, the input of the first stage 101 is connected to the output of the second stage 111 (via switch 103). The sample and hold circuit 102 of the first stage 101 samples VIN when a first clock signal Φ1 is high and holds the same when Φ1 is low. The sub-ADC 104 carries out a conversion of the input voltage VIN. The N-bit output D1 of the sub-ADC 104 is converted back to an analog voltage by the digital-to-analog converter 106 and then subtracted from the original input signal VIN by the summation circuit 108. The resulting error residue is then multiplied by 2N−1 in the multiplier 110 and fed as an analog input signal to the second stage 111. The second stage 111 operates in the same manner as the first stage 101, except that the sample and hold operation in the second stage 111 is controlled by a second clock signal Φ2 (in the same manner that the sample and hold operation in the first stage 101 is controlled by the first clock signal Φ1); the sub-ADC 114 of the second stage 111 has an N-bit output D2.
Since the sub-ADCs 104, 114 resolve the input with an accuracy of 2−N, a multiplication factor of 2N would let the error residue occupy the entire range of the sub-ADCs 104, 114 of the following stage. However, that would also require offset performance for the sub-ADCs 104, 114 in par with the resolution of the entire cyclic analog-to-digital converter 100. Otherwise, an offset in the sub-ADCs 104, 114 or the digital-to-analog converters 106, 116 would result in a faulty digital code and the error residue would exceed the range of the sub-ADCs 104, 114 of the following stage. Such an error cannot be recovered from and would result in missing codes. The most common solution to this problem is to introduce digital redundancy in the analog-to-digital converter 100.
There is one bit digital redundancy in the cyclic analog-to-digital converter 100 illustrated in FIG. 2 since the multiplication factor is 2N−1. This means that the error residue only occupies half the input range of the sub-ADCs 104, 114 of the following stage, and that only N−1 bits are effectively resolved per stage. A very common implementation is the 1.5 bits stage where the input range to the sub-ADCs 104, 114 is divided into three regions (1.5 bits). The multiplication factor is 2 and there are 2 digital output bits per stage (effectively 1.5 bits). With such an implementation, an offset in the bit transition points for the sub-ADCs 104, 114 of ±⅛ of the input range can be tolerated without resulting in missing codes.
The digital-to-analog converters 106, 116, error residue generation, and multiplication by 2 operation described above are often implemented with a switched capacitor circuit referred to as a multiplying digital-to-analog converter (MDAC). Switches are not shown for convenience purposes. Example configurations of two phases of an MDAC are illustrated in FIG. 3a. In FIG. 3a, the phase 1 MDAC configuration is labeled 220 and comprises two capacitors 222, 224 and an amplifier 226. The capacitors 222, 224 are connected to VIN in and are also connected to a negative input and the output of the amplifier 226. In FIG. 3a, the phase 2 MDAC configuration is labeled 230 and comprises capacitors 222, 224 and amplifier 226 connected to a digital-to-analog converter 106 instead of VIN. A digital code DIN is input into the digital-to-analog converter 106, which outputs VDAC to capacitor 224, which is connected to capacitor 222. The connection between the capacitors 222, 224 is connected to a negative input of amplifier 226, which outputs VO to capacitor 222. Capacitor 222 has a capacitance C1 while capacitor 224 has a capacitance C2. The transition from phase 1 to phase 2 yields an output VO equal to (1+C2/C1)VIN−(C2/C1)VDAC.
The 1.5 bits cyclic ADC stage (described above) should have a transfer function according to FIG. 3b. In FIG. 3b, VO is the output from the first stage 101 in phase n and VIN is the output from the second stage 111 in phase n−1. It should be appreciated that VIN could be the output from the first stage 101 in phase n and VO could be the output from the second stage 111 in phase n−1. The transfer function illustrated in FIG. 3b can be written as:
      v          o      ⁢                            =      {                                                                      2                ⁡                                  [                                                            v                      IN                                        -                                                                  V                        REF                                            2                                                        ]                                            ,                                                                          v                IN                            >                                                V                  REF                                4                                                                                                        2                ⁢                                                                  ⁢                                  v                  IN                                            ,                                                                                            -                                                            V                      REF                                        4                                                  ⁢                                  <                  _                                ⁢                                  v                  IN                                ⁢                                  <                  _                                ⁢                                                      V                    REF                                    4                                            =                                                                                          2                ⁡                                  [                                                            v                      IN                                        +                                                                  V                        REF                                            2                                                        ]                                            ,                                                                          v                IN                            <                              -                                                      V                    REF                                    4                                                                        ⁢              {                                                                                                  2                    ⁢                                          v                      IN                                                        -                                      V                    REF                                                  ,                                                                                      v                  IN                                >                                                      V                    REF                                    4                                                                                                                          2                  ⁢                                                                          ⁢                                      v                    IN                                                  ,                                                                                      -                                                            V                      REF                                        4                                                  ⁢                                  <                  _                                ⁢                                  v                  IN                                ⁢                                  <                  _                                ⁢                                                      V                    REF                                    4                                                                                                                                              2                    ⁢                                          v                      IN                                                        -                                      V                    REF                                                  ,                                                                                      v                  IN                                <                                  -                                                            V                      REF                                        4                                                                                          
From this transfer function it is clear that the multiplying digital-to-analog converter illustrated in FIG. 3a can be used in the cyclic analog-to-digital converter 100 if C1=C2 and the value of VDAC is one of −VREF, 0, or VREF. Cyclic analog-to-digital conversion would then be carried out according to FIG. 4, which illustrates example phases of a cyclic analog-to-digital converter 200 in operation. FIG. 4 is split into 3 sections, a first section representing phase 0 of a conversion cycle of the analog-to-digital converter 200, a second section representing odd phases 1, 3, 5, . . . of the conversion cycle and a third section representing additional even phases 2, 4, 6, . . . of the conversion cycle of the analog-to-digital converter 200.
In phase 0, the first stage 201 of cyclic analog-to-digital converter 200 is configured with MDAC 220, sub-ADC 104 and digital-to-analog converter 106; the second stage 211 of cyclic analog-to-digital converter 200 comprises capacitors 232, 234 and an amplifier 236 connected in the MDAC 230 configuration, sub-ADC 114 and digital-to-analog converter 116. The output from the sub-ADC 104 of the first stage 201 is D0 while the output of the sub-ADC 114 of the second stage 201 is DN. The cyclic analog-to-digital converter 200 then transitions from phase 0 to phase 1 (as shown by arrow A).
In phase 1, the first stage 201 of cyclic analog-to-digital converter 200 is configured with MDAC 220′, which includes capacitors 222, 224 connected between the output of the digital-to-analog converter 106 and the input of the second stage 211. As can be seen, the capacitors 222, 224 are arranged in the phase 2 MDAC configuration. The second stage 211 is configured with MDAC 230′, which includes capacitors 232, 234 connected in the MDAC phase 1 configuration. The output from the sub-ADC 104 of the first stage 201 is D0 while the output of the sub-ADC 114 of the second stage 201 is D1. The cyclic analog-to-digital converter 200 then transitions from phase 1 to phase 2 (as shown by arrow B).
In phase 2, the first stage 201 of cyclic analog-to-digital converter 200 is configured with MDAC 220, sub-ADC 104 and digital-to-analog converter 106; the second stage 211 of cyclic analog-to-digital converter 200 is configured with MDAC 230, sub-ADC 114 and digital-to-analog converter 116. The output from the sub-ADC 104 of the first stage 201 is D2 while the output of the sub-ADC 114 of the second stage 201 is D1. The cyclic analog-to-digital converter 200 then cycles through phases 3, 4, 5, 6, . . . (as shown by arrows C and B) until the last bit of the analog-to-digital converter's 200 resolution has been output.
Although the aforementioned cyclic analog-to-digital converter 200 works well, it is not without its shortcomings. For example, it is desirable to reduce power consumption and improve settling times and noise power in cyclic analog-to-digital converters, particularly those used in imagers.